VLSI

S.NO	PROJECT             CODE	TITLE	YEAR
AREA EFFICIENT
1.	IFVL01	High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels	2015
2.	IFVL02	An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis	2015
3.	IFVL03	Trade-offs for Threshold Implementations Illustrated on AES	2015
4.	IFVL04	A Modified Partial Product Generator for Redundant Binary Multipliers	2015
5.	IFVL05	Reviewing High-Radix Signed-Digit Adders	2015
6.	IFVL06	Critical-Path Analysis and Low-Complexity  Implementation  of the LMS Adaptive Algorithm	2014
		LOW POWER
7.	IFVL07	Implementation of Sub threshold Adiabatic Logic for Ultralow-Power Application	2015
8.	IFVL08	Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic	2015
9.	IFVL09	Exact and Approximate Algorithms for the Filter Design Optimization Problem	2015
10.	IFVL10	Ultralow-Energy Variation-Aware Design: Adder Architecture Study	2015
11.	IFVL11	Fault Tolerant Parallel Filters Based on Error Correction Codes	2015
12.	IFVL12	Area-Delay-Power Efficient Carry-Select Adder	2014
		HIGH SPEED
13.	IFVL13	Variable Latency Speculative Han-Carlson Adder	2015
14.	IFVL14	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications	2015
15.	IFVL15	Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}	2015
16.	IFVL16	Energy-Efficient Approximate Multiplication for Digital  Signal Processing and Classification Applications	2015
17.	IFVL17	An Optimized Modified Booth Recoder for Efficient Design of the  Add- Multiply  Operator.	2014
18.	IFVL18	Low-Latency Successive-Cancellation Polar Decoder Architectures Using      2-Bit Decoding.	2014
		QCA TECHNOLOGY
19.	IFVL19	Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover	2015
20.	IFVL20	Synthesis of Majority/Minority Logic Networks	2015
21.	IFVL21	Design and simulation of Turbo encoder in quantum-dot cellular automata	2015
22.	IFVL22	Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata.	2014
23.	IFVL23	Area-Delay Efficient Binary Adders in QCA.	2014
		DESIGN with TEST BENCH
24.	IFVL24	Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations	2015
25.	IFVL25	ERSFQ 8-Bit Parallel Adders  as a Process Benchmark	2015
26.	IFVL26	(4 + 2log n)ΔG Parallel Prefix Modulo-(2n − 3) Adder via Double Representation of Residues in [0, 2]	2015
		EDA TOOL (TANNER TOOL)
27.	IFVL27	Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology	2015
28.	IFVL28	Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications	2015
29.	IFVL29	Recursive Approach to the Design of a Parallel Self-Timed Adder	2015
30.	IFVL30	Low-Power Variation-Tolerant Nonvolatile Lookup Table Design	2015
31.	IFVL31	Finite State Machines With Input Multiplexing: A Performance Study	2015
32.	IFVL32	Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator	2014
33.	IFVL33	Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits	2014
		VLSI with MATLAB
34.	IFVL34	A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of  DCT	2015
35.	IFVL35	Design and Analysis of Approximate Compressors for Multiplication	2015
36.	IFVL36	An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders	2015
37.	IFVL37	Efficient coding scheme for fault Tolerant parallel filter	2015
38.	IFVL38	Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding	2015
39.	IFVL39	Improved 8-Point Approximate DCT for Image and  Video Compression Requiring Only 14 Additions	2014
40.	IFVL40	High-Throughput Multi standard Transform Core Supporting MPEG /H.264/VC-1 Using CSDA	2014